1. Field of the Invention
The invention relates to the field of high speed short-channel complementary MOS (CMOS) transistor structures and process of fabricating such CMOS transistor structures.
2. Description of the Prior Art
Complementary metal-oxide-semiconductor (CMOS) transistors are well-known in the art, and are often used in applications where low power consumption and high noise immunity are required. However, the channel lengths of either p-channel MOS transistors or n-channel MOS transistors of prior art CMOS transistors are generally determined by the precision of photolithographic and etching techniques during diffusion steps, and are practically limited to about four or five microns. Therefore, short-channel lengths of one micron are extremely difficult to obtained. Very high speed operations employing prior art CMOS integrated circuits have not been realized. In addition to the photolithographic limitation in achieving short-channel lengths, punch-through breakdown mechanism and short-channel effects in a short-channel device post severe problems in providing desired device characteristics.